In the field of semiconductor packaging, in order to realize the More Than Moore mode, 2.5D and 3D packaging have become one of the fastest -growing advanced packaging technologies.
In fact, technologies that can be the same as 2.5D and 3D packaging include: heterogeneous integration, fan -out type, FOWLP, FOPLP, silicon hole, glass packaging, packaging, packaging, packaging, packaging, packaging, packaging, packagingAntenna, co -seaweed optical devices, RDL and so on.These technologies are bringing greater performance improvement to the fields of artificial intelligence, high -performance computing (HPC), data centers, autonomous vehicles, 5G and consumer electronics.
However, there are some short -scale ruler inch. Lets take a look at some of the viewers views on 2.5D and 3D advanced packaging and related technologies.
Evolution of semiconductor packaging
The earliest semiconductor packaging is 1D PCB level, which has now developed to wafersGrade advanced 3D hybrid bonding combines high -energy efficiency indicators of a digital micrometer and a 1000GB/s bandwidth.
There are four key parameters leading this evolution: one is the power to optimize the efficiency;The requirements required by the HPC chip can be achieved smaller with 3D integration; the fourth is the cost, and the manufacturing efficiency is improved by continuously reducing alternative materials.
2.5D and 3D packaging technology incorporate various packaging processes.In 2.5D packaging, depending on the intermediary layer materials, it is divided into silicon -based, organic and glass -based intermediary layers; in 3D packaging, the development of micro pump technology further realizes a smaller spacing size.In addition, by adopting the mixed keymine technology (such as directly connecting CU-CU), the spacing size of single digits can be achieved, marking a major progress in the field.
Evolution of semiconductor packaging
2.5DThree keys of packaging
In fact, no matter which advanced package is, it will have its own advantages and disadvantages.2.5D packaging is mainly made of silicon, organic and new glass.On the silicon -based plate, the chip can be connected to the intermediary layer, and the intermediary layer and the chip can be connected by silicon -pores; organic packaging is used as a substrate, which has the characteristics of low cost and bending.In addition, glass substrates with high temperature and light transmission can also be used as packaging substrates.
Dr. Yu-Han Chang and Dr. James Jeffs of Idtechex believe that the silicon intermediary layer useThe bottom of the bottom is used in the form of a local silicon bridge, which is usually used in HPC integrated 2.5D packaging to satisfy the most fine routing function.However, compared with alternatives such as organic materials, silicon faces cost challenges and restrictions on packaging area in terms of materials and manufacturing.
In order to solve this problem, the form of local silicon bridges is increasing, and silicon is strategically used only in fine functions."It is expected that the silicon bridge structure will be used more, especially when the silicon intermediary layer is facing area restrictions," they said.
Organic materials have a dielectric constant below silicon, which helps reduce the delay of RC (resistance) in the packaging. It is a substitute for silicon more cost -effective.These advantages promote 2.5D packaging based on organic matter.
However, one of the main disadvantages of organic matter is that compared with silicon -based packaging, the reduction of the same horizontal interconnection function limits its adoption in HPC applications.In terms of cost, organic RDL (re -distribution layer) is suitable for cost -sensitive products. The board -level packaging will further use cost benefits, and glass packaging is expected to become a cheap alternative to silicon.
2.5D packaging technology development trend
The performance of semiconductor packaging needs to consider multiple aspects:
First is a dielectric material: as an important part of semiconductor packaging, its performance directly affects the electrical performance and reliability of the packaging packagingEssenceChoose a dielectric material with high insulation, low -agency electric constant and medium loss to help improve the packaging performance.
The second is RDL: RDL is a key technology in semiconductor packaging. It can re -distribute the chip pin to meet the needs of packaging.By optimizing the thickness, materials and techniques of the RDL layer, the electrical performance and reliability of the packaging can be improved.
L/S (line width and line spacing): L/S is a parameter describing the characteristics of interconnection in semiconductor packaging.Reducing L/S can increase interconnection density and improve packaging performance.However, too small L/S can cause difficulty and reliability problems, so weighing between the two.
Back size: The convex point is the connection point between the chip and the packaging substrate.Reducing the convex point size can improve the electrical performance and reliability of the packaging, and it is also necessary to ensure the strength of the convex point and the stability of the connection.
chip size and shape: reducing the chip size can increase the packaging density, but it also needs to consider the heat dissipation performance and electrical performance of the chip; the chip with complex shapes may increase the complexity of the packaging complicationDifficulty.
Packaging type: Choosing the right packaging type is also the key to improving semiconductor packaging performance.For example, 2.5D and 3D packaging technology can improve chip performance, reduce power consumption, reduce volume, and reduce costs.
Manufacturing process: Optimizing the manufacturing process can improve the reliability and stability of packaging.For example, adopting advanced materials, equipment and processes can reduce defects and adverse rates and improve production efficiency.
The two major technologies of 3D packaging
For 3D packaging, Dr. Yu-Han Chang and Dr. James JeffsIt is believed that the first important technology is the micro pump.Earlier, micro pump technology based on thermal pressure bonding (TCB) process has been relatively mature and has been used in various products.Its technical route lies in continuously expanding the spacing of convex points.However, there is a key challenge in this process, because the smaller welding ball size will lead to an increase in metal intervertebral compounds (IMC), reducing electrical and mechanical properties.
In addition, the tight contact gap may also cause the welding bridge to connect, and there is a chip failure risk during the return period.Due to the high resistance of welds and IMC, the application of high -performance component packaging is faced with restrictions.
The second important technology is the mixing key, including combining the combination of dielectric materials (SIO2) into the metal (CU) to create permanent connection.The spacing of the CU-CU hybrid key is less than 10 μm (usually about 1µm), and its advantages include extended I/O, increasing bandwidth, enhancing 3D vertical stacks, and increasing power efficiency. Because there is no bottom filling, it can reduce parasites and thermal resistanceEssenceThe challenge is the manufacturing complexity and higher cost of this advanced technology.
The development of convex point manufacturing technology
CU-CUThe mixing key is a kind of non -convex point -free bond. It uses the direct key between the copper metal and does not need to use the convex point or other intermediary layers.In the CU-CU hybrid bond, the direct keys between copper metals are achieved through surface treatment and thermal pressure bonding technology.
Compared with the traditional convex bonding method, the CU-CU mixing key does not need to make convex points, so it can simplify the manufacturing process, reduce costs and increase the packaging density.Provide more stable electrical connections and better thermal conductivity.
For example, the CU-CU hybrid back-back illuminating CMOS image sensor for Samsung mobile phone uses memory+logic 3D stacks, realizing the high bandwidth memory (HBM) of stacking DRAM nude (HBM)EssenceIts advantages are larger I/O and larger bandwidth, more 3D vertical stacks, high power efficiency, lack of filling to reduce parasites, and reduce thermal resistance.Of course, this method has a certain manufacturing difficulty and the cost is relatively high.
The minimum convex point spacing of different packaging technology
Who will drive the technology trend of advanced semiconductor packaging?
Compared with single -chip IC, advanced semiconductor packaging helps to speed up the listing of the product and reduce costs.Advanced interconnection technology can provide low power consumption, low latency and high bandwidth connection. At the same time, the benefits of integrated circuits are higher and the system performance is better. It can also integrate different silicon ICs or components in the same packaging.
HPC chip integration is a great driving force for advanced packaging.The processor-memory difference needs to increase the bandwidth of the memory. The HBM package of 2.5D can be done.Emerging AL training HPC also requires more bandwidth. Logically, 3D stack SRAM can further increase bandwidth, stacking can continue to reduce the 3D bond spacing to meet higher bandwidth requirements.
HPC chip integration trend
The length of the interconnection is very short, and the memory 3D stacks the logic or vice versa, which is considered the best way to achieve ultra -high bandwidth.However, its limitations include a large number of silicon -pass holes (TSV) used in logical IC for power and signals require a large number of occupied area, and the management logic IC has high cooling problems.
For these issues, there are two development paths: one is to use TSV to achieve 3D stacks, which are mainly used for memory to reduce the number of I/O of the logical IC; second, the development 2.5D 2.5DPackaging technology is to effectively dissipate heat from exposed logic IC.These short -term solutions can achieve homogeneous and heterogeneous integration before fully realizing the potential of 3D stacks.
Another big power is the data center server accelerator, including GPU small chip packaging (such as GPU+GPU, GPU+CACHE), GPU+HBM integration (GPU+HBM), FPGA small smallChip integration, etc.In 2022, the shipments of the relevant packaging unit were 19.2 million. According to forecasts, it will exceed seven times more than 2022 by 2034.
Data Center server accelerator packaging unit shipment trend
Future challenges of advanced packaging
In the future, the challenges of advanced packaging mainly come from some new technologies, such as glass packaging.In September 2023, Intel announced its glass -based test vehicle packaging, which caused great interest in people.The glass substrate has the characteristics of high temperature resistance and light transmission, including the adjustable thermal expansion coefficient (CTE), high size stability, and smooth and flat surface. These characteristics make it a very promising intermediary candidate.The wiring characteristics may be comparable to silicon.
However, although a large number of studies have shown the benefits of glass packaging, the scale of using it as a packaging substrate is still small.The manufacturing problem cannot be avoided. A key advantage of glass is its smooth and flat surface, which can be easier to deposit high -density RDL layers on the top.
However, several companies mentioned that the flatness of the glass substrate they purchased cannot be compared with silicon wafers.When the RDL layer is deposited on the top, the flatness is a huge challenge.There are also standardized issues, involving materials, crafts, equipment, testing and reliability.Only by establishing a standardized system can we ensure the quality and reliability of the product.
Another example is CPO (co -packaging optical) technology. It is a technology that encapsulates the light module and the battery chip together with the characteristics of low power consumption and high bandwidth.Its biggest challenge is the cost. In addition to the cost of optical components and R & D costs, it also includes the cost of BOM (material list) cost, assembly throughput cost and good rate optimization cost.
The most important thing is that as the demand for bandwidth continues to increase, the cost of fiber and sockets is getting higher and higher.The solution is to develop an ecosystem and optimize the design of optical components; strengthen industrial chain cooperation, optimize production processes, improve the throughput and output of optical fiber manufacturing, and reduce production costs.Of course, for glass packaging technology, this aspect is also not to be ignored.
