IT House November 13 news, technology media Techpowerup released a blog post yesterday (November 12), which reported that AMD announced the second -generation Versal Premium series adaptive SOC platform, will become a will become aThe FPGA industry is the first device to use CXL3.1 and PCIE GEN6 in hard IP and support LPDDR5 memory.
High -speed data access and processing
The second -generation Versal Premium series self -adaptation SOC platform to support the industrys fastest host interface CXL 3.1 and PCIeGen 6, the industrys leading high -bandwidth host CPU and accelerator connection.
Compared with FPGA that supports PCIe Gen 4 or Gen 5, PCIe Gen 6 can provide itThe line rate of 2 to 4 times, and CXL 3.1 running PCIE GEN 6 can provide double bandwidth of the CXL 2.1 device under similar latency, and enhanced architecture and consistency function.
Improve memory bandwidth and utilization rate
The second generation AMD Versal Premium series adaptive SOC can even high 8533 MB/s fastest LPDDR5 memory connection acceleration memory memoryBandwidth brings faster data transmission and real -time response.Compared with similar devices using LPDDR4/5 memory, this ultra -fast enhanced DDR memory can increase the hosting speed by 2.7 times higher.
Connection with the CXL memory extension module can make the total bandwidth be more than 2.7 times higher than the LPDDR5X memory alone.
Therefore, the second -generation Versal Premium series allows multiple accelerators to achieve scalable memory pools and extensions, thereby optimizing the use of memory and increasing bandwidth and capacity.
By dynamically allocated the memory pool for multiple devices, the second-generation Versal Premium series adaptive SOC aims to increase the use rate of multi-headed logic devices (MH-SLD) to make itIt can be run without architecture or switch, and supports up to two CXL hosts.
Strengthen data security
Enhanced security functions help the second -generation Versal Premium series can quickly and securely transmit data in the transmission and static state.It is the first FPGA device 6 supported by integrated PCIE® integrity and data encryption (IDE) in the hard IP.
CXL 3.1 and LPDDR5X memory will help meet the growing demand for real-time processing and storage.Salil Raje, senior vice president of AMD adaptive and embedded computing group, said the platform will help customers improve the utilization rate of system throughput and memory resources to achieve higher performance.
IT House briefly introduced the proprietary term appeared in this article:
On-site programmable logic door array (FPGA)
FPGA () is a semiconductor integrated circuit. The designer can be in the designer atProgramming and configuration of its logical circuit on the spot.
FPGA allows users to program programming at the hardware level, which can change its functions and structures as needed; FPGA usually has low power consumption, suitable for application scenarios with strict requirements on energy effectsEssence
CXL 3.1
Compute Express Link (CXL) is an open standard high -speed interconnection technology.It aims to provide efficient computing and storage solutions for modern data centers.
CXL 3.1 supports the data transmission rate of up to 64 GT/s, and introduces a trusted security protocol (TSP) to support virtualized trusted execution environment (TEE) in order to facilitateProcess confidential calculation workload.
PCIE GEN 6
PCIE GEN 6 (PCI Express 6.0) is the latest PCIE standard, transmission transmissionThe rate reaches 64 GT/s, which is almost twice that of PCIE 5.0 (32 GT/S).
PCIe 6.0 introduced PAM-4 (pulse amplitude modulation 4) technology. This technology further improves data transmission efficiency by transmitting more data bits in each signal cycle to further improve data transmission efficiencyEssence
PCIE 6.0 is particularly suitable for data centers, artificial intelligence (AI), machine learning (ML), and high -performance computing (HPC).
IT House attached the reference address
